1. Field of the Invention
This invention relates to a complementary metal oxide semiconductor (CMOS) voltage shifting logic circuit characterized by low direct current power consumption and high speed switching operation.
2. Description of the Prior Art
A level shifter circuit is conventionally employed to amplify a signal of a small voltage amplitude such as, for example, an ECL level to effect shifting of a voltage level of the signal to another signal of a greater amplitude.
Exemplary ones of conventional level shifter circuits are shown in FIGS. 1 and 2. In particular, FIG. 1 shows a conventional level shifter circuit which employs a flip-flop while FIG. 2 shows another conventional level shifter circuit which employs a current mirror.
In order to assure a high driving capacity for an output load of each of the level shifter circuits shown in Figs. 1 and 2, the current driving capacity of an element employed must necessarily be high. However, since dc current flows through the level shifter circuits, if the driving capacity is increased, then the dc consumption current is increased. Accordingly, the conventional level shifter circuits have a drawback that the operating speed depends upon a trade-off with the dc consumption current.